1. Field of the Invention
The present invention generally relates to semiconductor devices, and in particular, the present invention relates to partially depleted silicon-on-insulator (SOI) devices which include a mechanism for tuning the threshold voltage thereof.
2. Description of the Related Art
The partially depleted SOI device is a MOS transistor formed in a monocrystalline silicon substrate sitting above an insulating oxide layer, called a back oxide. The source/drain regions usually penetrate down to the back oxide. The channel region between the source and drain is doped so that the depletion region under the gate does not extend to the back oxide. This is the important difference between partially depleted and fully depleted SOI devices.
Silicon-on-insulator (SOI) devices are thus characterized by structures in which the Si device layers are formed over an insulating film. FIG. 1 illustrates an exemplary configuration of such a device.
The device of FIG. 1 includes an nfet 102 and a pfet 104 formed within a layer 106. The layer 106 is located along an oxide layer 108 formed atop a p+ bulk material 110. The nfet 102 includes source and drain n-regions 112 and 114, a p-region 116, and a gate electrode 118. Likewise, the pfet 104 includes source and drain p-regions 120 and 122, an n-region 124, and a gate electrode 126. SOI devices of this type are characterized by low parasitic capacitances, as well as high dielectric isolation of the on-chip components.
A "fully depleted" SOI device is shown in FIG. 2. Here, the device is configured such that the depletion regions 228 extend completely down to the interface with the oxide layer 208. This is done, for example, by making the layer 206 much thinner than the corresponding layer 306 of the partially depleted device shown in FIG. 3 and discussed below. The structure is otherwise similar to that of the partially depleted device, and includes an nfet 202 having source and drain n-regions 212 and 214, a p-type channel region 216, and a gate 218, and a pfet 204 having source and drain p-regions 220 and 222, an n-type channel region 224, and a gate 226. The substrate 210 is tied to a fixed potential such as ground.
A "partially depleted" SOI device refers to a structure in which the depletion region of the transistors does not extend all the way down to the oxide layer. An example of this is shown in FIG. 3. Here, the layer 306 is of sufficient thickness and the n-regions 312 and 314 are appropriately configured (e.g., through use of source-drain extensions) such that the depletion region 328 is spaced from the upper surface of the oxide layer 308, i.e., only a portion of the p-region 316 is depleted.
The non-depleted region between the source 312 and drain 314 is called the body or bulk. In conventional partially depleted SOI, the body is left floating or is connected to the source of the transistor. In another alternative, known as dynamic threshold MOS (DTMOS), the body is connected to the gate. This causes the threshold to be higher when the device is off than when it is on, which decreases the off-state leakage and increases the on-state current. Referring again to FIG. 3, a body contact 330 is embedded in the p-region 316, below the depletion region 328. Also, as shown, the body contact 330 is electrically tied to the gate electrode 318. As such, when the gate potential is turned on, the potential of the p-region 316 below the depletion region 328 (i.e., the "bulk region") is pulled up, whereby the bulk potential of the device tracks the gate potential. This results in a forward biasing of the bulk which in turn decreases the threshold voltage of the device.
There are a number of factors which contribute to the magnitude of an SOI device's threshold voltage. For example, to set a device's threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a device's threshold voltage by a few tens or even hundreds of a millivolt. Further, dimensional variations, charge trapping in the materials and interfaces, and environmental factors such as operating temperature fluctuations can shift the threshold voltage. Still further, low threshold devices may leak too much when their circuits are in a sleep or standby mode. Thus, particularly for low-threshold devices, it is desirable to provide a mechanism for tuning the threshold voltage to account for these and other variations.